The .NET Design Pattern Framework 4.5 is actually 10 products in one -- each filled with .NET code and information you will not find anywhere else -- and each working together, ready to give your apps, your projects, and your career a boost. They are: 69 Comprehensive .NET 4.5 GoF Design Pattern Projects 23 Valuable UML Diagrams in Visio format 3-Tier / N-Tier Pattern and Practices based Architectures Reference Application: ASP.NET MVC Patterns Reference Application: ASP.NET Web Forms Patterns Reference Application: Windows Forms Patterns Reference Application: WPF Patterns NEW Art Shop -- A fully functional, real-world e-commerce Web App NEW SparkTM -- A rapid application development (RAD) platform & more... Printable PDF documents for all Projects & Patterns Our most recent release, Design Pattern Framework 4.5, has been enhanced with the latest insights into building apps using modern architectures, patterns, and best practices. These include MVC 4, SimpleMembership, OAuth with Facebook, REST, Active Record Pattern, CQRS Pattern, Repository and Unit-of-Work Patterns, and more. We're particularly excited about the addition of our new SparkTM technology. Spark is a RAD (rapid application development) platform that helps you deliver .NET applications faster and better than ever before. Continue reading to learn more.

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Khalil写的非线性系统理论，经典！这是第二版的。

Hands-On Machine Learning with Scikit-Learn and TensorFlow: Concepts, Tools, and Techniques to Build Intelligent Systems by Aurélien Géron English | 13 Mar. 2017 | ASIN: B06XNKV5TS | 581 Pages | AZW3 | 21.66 MB Through a series of recent breakthroughs, deep learning has boosted the entire field of machine learning. Now, even programmers who know close to nothing about this technology can use simple, efficient tools to implement programs capable of learning from data. This practical book shows you how. By using concrete examples, minimal theory, and two production-ready Python frameworks—scikit-learn and TensorFlow—author Aurélien Géron helps you gain an intuitive understanding of the concepts and tools for building intelligent systems. You’ll learn a range of techniques, starting with simple linear regression and progressing to deep neural networks. With exercises in each chapter to help you apply what you’ve learned, all you need is programming experience to get started. Explore the machine learning landscape, particularly neural nets Use scikit-learn to track an example machine-learning project end-to-end Explore several training models, including support vector machines, decision trees, random forests, and ensemble methods Use the TensorFlow library to build and train neural nets Dive into neural net architectures, including convolutional nets, recurrent nets, and deep reinforcement learning Learn techniques for training and scaling deep neural nets Apply practical code examples without acquiring excessive machine learning theory or algorithm details

Contents About This Book The MindShare Architecture Series.......................................................................................1 Organization of This Book.......................................................................................................2 Who Should Read This Book ..................................................................................................3 Prerequisite Knowledge...........................................................................................................4 Documentation Conventions...................................................................................................4 Hex Notation.......................................................................................................................4 Binary Notation....................................................................................................................4 Decimal Notation.................................................................................................................4 Signal Name Representation..............................................................................................5 Identification of Bit Fields...................................................................................................5 We Want Your Feedback ..........................................................................................................5 E-Mail/Phone/FAX ............................................................................................................5 Bulletin Board.......................................................................................................................6 Mailing Address ..................................................................................................................6 Chapter 1: 80486 Overview System Performance Prior to the 80486..................................................................................7 The Memory Bottleneck ...........................................................................................................7 The Static Ram, or SRAM, Solution...................................................................................8 The External Cache Solution ..............................................................................................8 Advantage: Reduces Many Memory Accesses to Zero Wait States.......................8 Disadvantage: Memory Accesses Still Bound By Bus Speed..................................8 The 80486 Solution: Internal Code/Data Cache ..............................................................9 Faster Memory Accesses..............................................................................................9 Frees Up the Bus...........................................................................................................9 The Floating-Point Bottleneck ................................................................................................9 The 80386/80387 Solution ................................................................................................10 The 80486 Solution: Integrate the FPU............................................................................10 The 80486 Microarchitecture..................................................................................................10 The Intel Family of 486 Processors .......................................................................................12 80486 System Architecture vi Chapter 2: Functional Units The 80486 Functional Units....................................................................................................13 Introduction.......................................................................................................................13 The 80486 Bus Unit............................................................................................................15 The 80486 Cache Unit........................................................................................................15 The Instruction Pipeline/Decode Unit ...........................................................................16 Instruction Prefetch ....................................................................................................17 Two-Stage Instruction Decode..................................................................................18 Execution .....................................................................................................................18 Register Write-Back....................................................................................................18 The Control Unit ................................................................................................................18 The Floating-Point Unit ....................................................................................................19 The Datapath Unit .............................................................................................................19 The Memory Management Unit (MMU)........................................................................20 Chapter 3: The Hardware Interface Hardware Interface..................................................................................................................21 General ...............................................................................................................................21 Clock .........................................................................................................................................23 Address.....................................................................................................................................23 Data Bus....................................................................................................................................24 Data Bus Parity.........................................................................................................................25 Bus Cycle Definition...............................................................................................................26 Bus Cycle Control ....................................................................................................................27 Burst Control ............................................................................................................................28 Interrupts..................................................................................................................................28 Bus Arbitration........................................................................................................................29 Cache Invalidation ..................................................................................................................30 Cache Control ...........................................................................................................................30 Numeric Error Reporting........................................................................................................32 Bus Size Control.......................................................................................................................32 Address Mask...........................................................................................................................33 SL Technology.........................................................................................................................33 Boundary Scan Interface ........................................................................................................34 Upgrade Processor Support ...................................................................................................35 Chapter 4: The 486 Cache and Line Fill Operations The 486 Caching Solution ......................................................................................................37 The 486 Internal Cache......................................................................................................37 The Advantage of a Level 2 Cache..................................................................................38 The 486 with an L2 Look-Through Cache ...........................................................................38 Contents vii Handling of I/O Reads .....................................................................................................40 Handling of I/O Writes ....................................................................................................40 Handling of Memory Reads.............................................................................................40 Handling of Memory Writes ............................................................................................41 Handling of Memory Reads by Another Bus Master ...................................................41 When a Write-Through Policy is Used ....................................................................42 When a Write-Back Policy is Used...........................................................................42 Handling of Memory Writes by Another Bus Master ..................................................42 When a Write-Through Policy is Used ....................................................................43 When a Write-Back Policy is Used...........................................................................43 The Bus Snooping Process .....................................................................................................45 Summary of the L2 Look-Through Cache Designs ...........................................................45 The 486 with an L2 Look-Aside Cache ................................................................................46 Anatomy of a Memory Read..................................................................................................48 The Internal Cache's View of Main Memory .................................................................48 L1 Memory Read Request ................................................................................................49 The Structure of the L1 Cache Controller.......................................................................49 Set the Cache Stage............................................................................................................50 The Cache Look-Up...........................................................................................................52 The Bus Cycle Request ......................................................................................................52 Memory Subsystem Agrees to Perform a Line Fill .......................................................54 Cache Line Fill Defined.....................................................................................................55 Conversion to a Cache Line Fill Operation ....................................................................56 L2 Cache's Interpretation of the Memory Address .......................................................56 The L2 Cache Look-Up .....................................................................................................57 The Affect of the L2 Cache Read Miss on the Microprocessor ....................................57 Organization of the DRAM Main Memory....................................................................57 The Cache Line Fill Transfer Sequence...........................................................................58 The First Doubleword Is Read from DRAM Memory ..................................................59 First Doubleword Transferred to the L2 Cache and the 80486 Microprocessor .................................................................................................59 Memory Subsystem's Treatment of the Next Three Doubleword Addresses ....................................................................................................60 Transfer of the Second Doubleword to the Microprocessor ........................................60 Memory Subsystem Latching of the Third and Fourth Doublewords .......................61 Transfer of the Third Doubleword..................................................................................61 The Beginning of the End .................................................................................................62 Transfer of the Fourth and Final Doubleword...............................................................62 Internal Cache Update ......................................................................................................62 Summary of the Memory Read........................................................................................64 Burst Transfers from Four-Way Interleaved Memory ......................................................64 Burst Transfers from L2 Cache..............................................................................................66 80486 System Architecture viii The Interrupted Burst .............................................................................................................67 Cache Line Fill Without Bursting.........................................................................................69 Internal Cache Handling of Memory Writes......................................................................73 Invalidation Cycles (486 Cache Snooping) .........................................................................73 L1 and L2 Cache Control ........................................................................................................74 Chapter 5: Bus Transactions (Non-Cache) Overview of 486 Bus Cycles...................................................................................................77 Bus Cycle Definition...............................................................................................................78 Interrupt Acknowledge Bus Cycle .......................................................................................79 Special Cycles..........................................................................................................................79 Shutdown Special Cycle ...................................................................................................80 Flush Special Cycle............................................................................................................80 Halt Special Cycle..............................................................................................................80 Stop Grant Acknowledge .................................................................................................81 Write-Back Special Cycle ..................................................................................................81 Non-Burst Bus Cycles .............................................................................................................81 Transfers with 8-,16-, and 32-bit Devices ............................................................................82 Address Translation..........................................................................................................82 Data Bus Steering...............................................................................................................84 Non-Cacheable Burst Reads ..................................................................................................85 Non-Cacheable Burst Writes .................................................................................................87 Locked Transfers......................................................................................................................89 Pseudo-Locked Transfers .......................................................................................................89 Transactions and BOFF# (Bus Cycle Restart) .....................................................................90 The Bus Cycle State Machine................................................................................................91 I/O Recovery Time...................................................................................................................92 Write Buffers ............................................................................................................................93 General ...............................................................................................................................93 The Write Buffers and I/O Cycles...................................................................................94 Chapter 6: SL Technology Introduction to SL Technology Used in the 486 Processors.............................................95 System Management Mode (SMM) .....................................................................................96 System Management Memory (SMRAM)......................................................................98 The SMRAM Address Map.......................................................................................98 Initializing SMRAM.................................................................................................101 Changing the SMRAM Base Address....................................................................101 Entering SMM..................................................................................................................101 The System Asserts SMI ..........................................................................................101 Back-to-Back SMI Requests..............................................................................102 SMI and Cache Coherency...............................................................................102 Contents ix Pending Writes are Flushed to System Memory..................................................102 SMIACT# is Asserted (SMRAM Accessed)...........................................................103 Processor Saves Its State ..........................................................................................103 Auto-HALT Restart...........................................................................................105 SMM Revision Identifier ..................................................................................105 SMBASE Slot ......................................................................................................106 I/O Instruction Restart .....................................................................................106 The Processor Enters SMM .....................................................................................107 Address Space...........................................................................................................108 Exceptions and Interrupts .......................................................................................108 Executing the SMI Handler ............................................................................................109 Exiting SMM.....................................................................................................................109 Processor’s Response to RSM..................................................................................109 State Save Area Restored.........................................................................................110 Maintaining Cache Coherency When SMRAM is Cacheable.............................111 486 Clock Control...................................................................................................................111 The Stop Grant State........................................................................................................111 Stop Clock State ...............................................................................................................113 Auto-HALT Power Down ..............................................................................................113 Stop Clock Snoop State ...................................................................................................114 Chapter 7: Summary of Software Changes Changes to the Software Environment..............................................................................115 Instruction Set Enhancements.............................................................................................116 The Register Set .....................................................................................................................117 Base Architecture Registers............................................................................................117 The System-Level Registers............................................................................................119 Control Register 0 (CR0)..........................................................................................120 Cache Disable (CD) and Not Write-Through (NW) .....................................121 Alignment Mask (AM)......................................................................................121 Write-Protect (WP) ............................................................................................122 Numeric Exception (NE) ..................................................................................122 Control Register 2 (CR2)..........................................................................................122 Control Register 3 (CR3)..........................................................................................123 Control Register 4 (CR4)..........................................................................................123 Global Descriptor Table Register (GDTR).............................................................124 Interrupt Descriptor Table Register (IDTR) ..........................................................124 Task State Segment Register (TR)...........................................................................124 Local Descriptor Table Register (LDTR)................................................................124 Virtual Paging ..................................................................................................................125 The Floating-Point Registers ...................................................................................126 The Debug and Test Registers ................................................................................128 80486 System Architecture x Chapter 8: The 486SX and 487SX Processors Introduction to the 80486SX and 80487SX Processors.....................................................131 The 486SX Signal Interface ..................................................................................................132 Register Differences..............................................................................................................132 Chapter 9: The 486DX2 and 486SX2 Processors The Clock Doubler Processors ............................................................................................135 Chapter 10: The Write Back Enhanced 486DX2 Introduction to the Write Back Enhanced 486DX2 ..........................................................137 Advantage of the Write-Back Policy ..................................................................................138 The Write-Through Policy..............................................................................................138 The Write-Back Policy.....................................................................................................139 Signal Interface ......................................................................................................................139 New Signals......................................................................................................................139 Existing Signals with Modified Functionality..............................................................141 The MESI Model....................................................................................................................141 Write Back Enhanced 486DX2 System without an L2 Cache.........................................144 Cache Line Fill..................................................................................................................144 Bus Master Read — Processor Snoop ...........................................................................146 Bus Master Write — Processor Snoop ..........................................................................148 Write Back Enhanced 486DX2 System with an L2 Cache...............................................150 The L2 Cache with a Write-Through Policy.................................................................151 The L2 Cache with a Write-Back Policy........................................................................152 Snoop Cycle During Cache Line Fill .............................................................................152 Special Cycles.........................................................................................................................155 Clock Control.........................................................................................................................156 Chapter 11: The 486DX4 Processor Primary Feature of the 486DX4 Processor .........................................................................159 Clock Multiplier ....................................................................................................................159 16KB Internal Cache..............................................................................................................160 5vdc Tolerant Design ............................................................................................................162 Glossary..................................................................................................................................165 Index........................................................................................................................................183 Figures xi Figure 1-1. Subsystems Integrated into the 80486 ................................................................ 11 Figure 2-1. 80486 Microarchitecture ....................................................................................... 14 Figure 2-2. The Elements Comprising the 80486 Bus Unit .................................................. 16 Figure 2-3. 80486 Instruction Pipeline.................................................................................... 17 Figure 3-1. 80486 Pin Designations......................................................................................... 22 Figure 4-1. The 486 Processor with an L2 Look-Through cache........................................ 39 Figure 4-2. The 80486 with a Look-Aside External Cache................................................... 47 Figure 4-3. The Structure of the L1 Cache ............................................................................. 51 Figure 4-4. Internal Cache Interpretation of the Memory Address.................................... 52 Figure 4-5. Memory Address at the Start of the Bus Cycle ................................................. 53 Figure 4-6. Cache Line Fill with Bursting .............................................................................. 54 Figure 4-7. 64-Bit Interleaved Memory Architecture ........................................................... 58 Figure 4-8. The LRU Algorithm .............................................................................................. 63 Figure 4-9. 4-way Interleaved Memory Designed to Support Burst Transfers. ............... 65 Figure 4-10. Burst Timing from 4-way Interleaved Memory............................................. 66 Figure 4-11. Burst Timing from L2 Cache.............................................................................. 67 Figure 4-12. The Interrupted Burst......................................................................................... 69 Figure 4-13. Non-Burst Cache Line Fill.................................................................................. 72 Figure 4-14. Cache Invalidation Cycle ................................................................................... 74 Figure 5-1. Example of Non-Burst Cycle Timing.................................................................. 82 Figure 5-2. Address Translation for 8, 16, and 32-bit Devices ............................................ 83 Figure 5-3. System Logic Used to Perform Data Bus Steering............................................ 84 Figure 5-4. Non-Cacheable Burst Read Bus Cycle................................................................ 86 Figure 5-5. Non-Cacheable Burst Write Bus Cycle............................................................... 88 Figure 5-6. 80486 Bus Cycle States.......................................................................................... 91 Figure 6-1. Address Space Available to Processor when Operating in Different Modes................................................................................................. 97 Figure 6-2. Sample Layout of SMM Memory........................................................................ 99 Figure 6-3. Typical PC Memory Map (SMM Disabled versus SMM Enabled)................. 100 Figure 6-4. The Processor’s SMM State-Save Map ............................................................... 104 Figure 6-5. SMM Revision Identifier Definition ................................................................... 105 Figure 6-6. Stop Clock State Diagram .................................................................................... 112 Figure 7-1. The BSWAP Instruction........................................................................................ 117 Figure 7-2. 80486 Base Architecture Registers ...................................................................... 118 Figure 7-3. 486 EFlags Register Definition............................................................................. 119 Figure 7-4. 80486 System Registers......................................................................................... 120 Figure 7-5. Bit definition for CR0............................................................................................ 121 Figure 7-6. Format of CR3........................................................................................................ 123 Figure 7-7. Format of CR4........................................................................................................ 124 Figure 7-8. The 80486 Floating-Point Registers..................................................................... 128 Figure 7-9. The 80486 Debug and Test Registers .................................................................. 129 80486 System Architecture xii Figure 10-1. Example of System with Write Back Enhanced 486DX2 (no L2 Cache)............................................................................................................................ 145 Figure 10-2. Example Cache Line Fill — Write-Back Mode Enabled................................. 146 Figure 10-3. External Snoop Performed by Enhanced Write Back 486DX2 Processor ..................................................................................................................... 149 Figure 10-4. Write Back Enhanced 486 with Look-Through L2 Cache.............................. 150 Figure 10-5. Cache Line Fill with External Snoop ................................................................ 154 Figure 10-6. Stop Clock State Machine for Enhanced Bus Mode ....................................... 156 Figure 11-1. Organization of the 486DX4 Internal Cache.................................................... 161

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《JUnit实战(第2版)》从认识JUnit、不同的测试策略、JUnit与构建过程、JUnit扩展4个方面，由浅入深、由易到难地对JUnit展开了系统的讲解，包括探索JUnit的核心、软件测试原则、测试覆盖率与开发、使用stub进行粗粒度测试、使用mock objects进行测试、容器内测试、从Ant中运行JUnit测试、从Maven2中运行JUnit测试、持续集成工具、表示层的测试、Ajax测试、使用Cactus进行服务器端的Java测试、测试JSF应用程序、测试OSGi组件、测试数据库访问、测试基于JPA的应用程序、JUnit的其他用法等内容。 《JUnit实战(第2版)》不仅仅介绍了使用JUnit框架测试项目必须掌握的核心概念，还指导读者如何使用JUnit框架编写自己的测试用例，并针对在编写代码的过程中如何使得代码可测试给出建议。《JUnit实战(第2版)》还介绍了基础的软件开发原则，如测试驱动开发（TDD）等，以便指导用户如何使用不同的工具来测试典型Java EE应用程序的每一层。此外，《JUnit实战(第2版)》也提供了几个附录，以帮助读者快速转换到最新版本的JUnit，并且能够轻松地集成自己喜欢的IDE。