24秒计时器 VHDL
entity timer is
port(
clk : in std_logic;
rst : in std_logic;
pause : in std_logic;
hit : in std_logic;
sec1 : out std_logic_vector(5 downto 0);
sec2 : out std_logic_vector(7 downto 0);
sec1_pause : out std_logic_vector(5 downto 0);
sec2_pause : out std_logic_vector(7 downto 0)
);
end timer;
2021-10-26 16:59:27
2KB
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